module regCC 
(
input           clk,
input           rst_n,
input   [2:0]   e_alucc,
input           e_setcc,
output  reg [2:0]   e_cc
   );

//[2]--ZF-Zero,[1]-SF-Sign,[0]-OF-Overflow   
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        e_cc <= 3'b100;
    end else if(e_setcc) begin
        e_cc <= e_alucc;
    end
end

endmodule
